1. Field of the Invention
The present invention is generally related to semiconductor devices and manufacturing processes, and, more particularly, to a method of forming metal silicide regions on a gate electrode and above the source/drain regions of a semiconductor device.
2. Description of the Related Art
In standard semiconductor processing methods, a salicide forming process (self-aligned silicide forming process) is used for simultaneously forming metal silicide regions on the gate electrode and the source/drain regions of a semiconductor device. FIGS. 1A-1C show one example of this prior art salicide forming process.
FIG. 1A shows a cross-section of a semiconductor device 20 prior to the formation of the metal silicide regions. The illustrative semiconductor device 20 has been formed by conventional techniques. The semiconductor device 20 is comprised of a gate insulation layer 5, a gate electrode 4, sidewall spacers 6, and source/drain regions 3. The various components may be formed by a variety of known techniques. For example, the trench isolations 2 may be formed by traditional trench isolation techniques. The gate electrode 4 and gate insulation layer 5 may be manufactured by forming layers of the appropriate materials, and, thereafter, patterning the layers using known photolithographic and etching techniques. The sidewall spacers 6 may be formed by depositing a layer of the spacer material, and, thereafter, performing an anisotropic etching process. The source/drain regions 3 may be formed by one or more ion implantation steps in which dopant atoms are implanted into the substrate 1.
FIG. 1B depicts the first step of the process for forming metal silicide regions on the gate electrode 4 and the source/drain regions 3. In this step, a thin refractory metal layer 7 is blanket deposited above the partially-formed semiconductor device. An initial rapid thermal anneal (RTA) process is performed for forming a metastable metal silicide in the regions where the refractory metal layer 7 is in direct contact with an underlying silicon layer. During the initial RTA process, the metal atoms of the refractory metal layer 7 penetrate into the underlying silicon layers and combine with the silicon. The penetration depth is controlled by the initial thickness of the refractory metal layer, and the temperature and time of the initial RTA process.
In the next step, as shown in FIG. 1C, the portion of the refractory metal layer 7 which has not been transformed into metastable metal silicide layers during the initial RTA process is removed by a metal etching process, such as a dilute acid bath. After etching, the gate silicide region 8 on top of the gate electrode 4 and the source/drain silicide regions 9 covering the source/drain regions 3 are exposed. Then, a final RTA process is performed to transform the initially formed metastable metal silicide regions 8, 9 into the chemically stable form of the metal silicide.
The thickness of the metal silicide regions 9 formed above the source/drain region 3 is adjusted in order to maintain the integrity of the shallow source/drain junctions. Since the metal silicide regions 8, 9 are formed in the same salicide process, this results in a relatively thin, and therefore less conductive, gate metal silicide region 9. Therefore, the ability to optimize the gate sheet resistance is limited. Moreover, the lower conductivity of the gate electrode 4, as provided by this conventional method, tends to limit the switching speed of the semiconductor device.
The present invention is directed to a method of making a semiconductor device that solves, or at least reduces, some or all of the aforementioned problems.
In one aspect, the present invention is directed to a method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a semiconducting substrate, the gate stack being comprised of a gate electrode and a protective layer, forming a plurality of source/drain regions in the substrate, and forming a first metal silicide region above each of the source/drain regions. The method further comprises removing the protective layer from above the gate electrode and forming a second metal silicide region above the gate electrode.
In another aspect, the method comprises forming a gate stack comprised of a gate electrode forming a plurality of source/drain regions in the substrate adjacent the gate stack, and forming a first metal silicide region on each of the source/drain regions. The method further comprises forming a layer of silicon dioxide on each of the first metal silicide regions by performing an anneal process in an oxygen-containing environment and forming a second metal silicide region above the gate electrode after forming the layer of silicon dioxide above each of the source/drain regions.